Staff Profile

My profile on Google Scholar

Projects

• Next Generation Energy-Harvesting Electronics - holistic approach
  
• Next Generation of interconnection technology for multiprocessor SoC (NEGUS)
  
• Secure Circuit Design (SCREEN)
  
• Secure Design Flow (SURE)
  
• Synthesis and TEsting of Low-Latency Asynchronous circuits (STELLA)
  
• Hazard-Free Arbiter Design
  

Other research activities

• COST Action IC1204 "TRUDEVICE" 
• COST Action IC1103 "MEDIAN"
• RIIF Reliability Information Interchange Format work group
  
• Chairman of the IEEE International Workshop on Impact of Low-Power design on Test and Reliability (fringe to European Test Symposium) - LPonTR 2009-2011
• Guest Editor for the special section of Journal of Low Power Electronics (JOLPE)
  
• Chair of tutorials of 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008, Newcastle http://async.org.uk/async2008/
  
• TPC member of IEEE International On-Line Testing Symposium
  
• TPC member of IEEE International Symposium on Asynchronous Circuits and Systems
  
• TPC member of UK Embedded Forum
  
• Local organiser of 3rd UK Embedded Forum, 2007 http://async.org.uk/ukef07/
  
• Referee for Integration, the VLSI Journal
• Referee for Microelectronics Journal
• Referee for IET Computers & Digital Techniques Journal
  

• Abufalgha MA, Bystrov A. Derivation of the reliability metric for digital circuits. In: Proceedings of the European Test Symposium (ETS). 2017, Limassol, Cyprus: Institute of Electrical and Electronics Engineers Inc.
• Abufalgha MA, Bystrov A. Design-time reliability evaluation for digital circuits. In: 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS 2017). 2017, Thessaloniki, Greece: IEEE.
• Fakhrey H, Boussakta S, Tiwari R, Al-Mathehaji Y, Bystrov A. Location-dependent key management protocol for a WSN with a random selected cell reporter. In: IEEE International Conference on Communications (ICC 2015). 2015, London: IEEE.
• Al Yaman M, Al-Atabany W, Bystrov A, Degenaar P. FPGA design for dual-spectrum Visual Scene Preparation in Retinal Prosthesis. In: 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). 2014, Chicago, Illinois, USA: IEEE.
• Rutter N, Boussakta S, Bystrov A. Assessment of the One-Dimensional Generalized New Mersenne Number Transform for Security Systems. In: 77th IEEE Vehicular Technology Conference (VTC Spring). 2013, Dresden, Germany: IEEE.
• Al-Yaman M, Ghani A, Bystrov A, Degenaar P, Maaskant P. FPGA design of a pulse encoder for optoelectronic neural stimulation and recording arrays. In: IEEE Biomedical Circuits and Systems Conference (BioCAS). 2013, Rotterdam, The Netherlands: IEEE.
• Ni CX, Al Tarawneh Z, Russell G, Bystrov A. Modelling and Analysis of Manufacturing Variability Effects from Process to Architectural Level. In: INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION. 2013, HEIDELBERGER PLATZ 3, D-14197 BERLIN, GERMANY: SPRINGER-VERLAG BERLIN.
• Bystrov A. Selected Articles from the IEEE LPonTR 2012 Workshop. Journal of Low Power Electronics 2013, 9(1), 118-118.
• Docherty J, Bystrov A, Yakovlev A. Simulation testing of a real-time heuristic scheduler with automotive benchmarks. International Journal of Simulation: Systems, Science and Technology 2013, 14(3), 1-11.
• Docherty J, Bystrov A, Yakovlev A. Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks. In: 15th IEEE International Conference on Computer Modelling and Simulation (UKSim). 2013, Cambridge, UK.
• Docherty J, Bystrov A, Yakovlev A. Simulation Testing of a Real-Time Heuristic Scheduler with Automotive Benchmarks. In: UKSIM-AMSS 15TH INTERNATIONAL CONFERENCE ON COMPUTER MODELLING AND SIMULATION (UKSIM 2013). 2013, 345 E 47TH ST, NEW YORK, NY 10017 USA: IEEE.
• Burns F, Bystrov A, Koelmans A, Yakovlev A. Design and security evaluation of balanced 1-of-n circuits. IET Computers and Digital Techniques 2012, 6(2), 125-135.
• Julai N, Yakovlev A, Bystrov A. Error detection and correction of single event upset (SEU) tolerant latch. In: IEEE 18th International On-Line Testing Symposium (IOLTS). 2012, Sitges, Spain: IEEE.
• Docherty J, Bystrov A, Yakovlev A. Identification of Key Energy Harvesting Parameters through Monte Carlo Simulations. In: 14th International Conference on Computer Modelling and Simulation (UKSim). 2012, Cambridge: IEEE.
• Ni C, Al Tarawneh Z, Russell G, Bystrov A. Modelling and analysis of manufacturing variability effects from process to architectural level. In: PATMOS 2012 International Workshop on Power and Timing Modeling, Optimization and Simulation. 2012, Newcastle upon Tyne, UK: Springer.
• Murphy J, O'Neill M, Burns F, Bystrov A, Yakovlev A, Halak B. Self-Timed Physically Unclonable Functions. In: 5th International Conference on New Technologies, Mobility and Security (NTMS). 2012, Istanbul, Turkey: IEEE.
• Ni CX, Russell G, Bystrov A. Statistical Delay Modelling of Manufacturing Process Variations at System Level. In: 10th IEEE International New Circuits and Systems Conference (NEWCAS). 2012, Montreal, Canada: IEEE.
• Baz A, Shang DL, Xia F, Yakovlev A, Bystrov A. Improving the Robustness of Self-timed SRAM to Variable Vdds. In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation: 21st International Workshop (PATMOS). 2011, Madrid, Spain: Springer.
• Burns F, Bystrov A, Koelmans A, Yakovlev A. Security Evaluation of Balanced 1-of-n Circuits. IEEE Transactions on VLSI Systems 2011, 19(11), 2135-2139.
• Zeidler S, Bystrov A, Krstic M, Kraemer R. On-line testing of bundled-data asynchronous handshake protocols. In: 16th IEEE International On-Line Testing Symposium (IOLTS). 2010, Corfu, Greece: IEEE.
• Bystrov A. Selected Peer-Reviewed Articles from the LPonTR 2009 Workshop. Journal of Low Power Electronics 2010, 6(2), 325-325.
• D'Alessandro C, Bystrov A, Yakovlev A. Implementation of a phase-encoding signalling prototype chip. In: 34th European Solid-State Circuits Conference (ESSCIRC 2008). 2008, Edinburgh, UK: IEEE.
• Kinniment D, Koelmans A, Fei X, Bystrov A, Chester G, Carloni L, Russell G, Roncken M, Vivet P, Murali S, Clark I, Moore S, Yakovlev A, Bainbridge J, Bertozzi D, Goossens K. Message from General Chairs. In: NOCS 2008: Second International Symposium on Networks-on-Chip. 2008, Newcastle University: IEEE Computer Society.
• D'Alessandro CS, Shang D, Bystrov A, Yakovlev AV, Maevsky O. Phase-encoding for on-chip signalling. IEEE Transactions on Circuits and Systems I: Regular Papers 2008, 55(2), 535-545.
• Bystrov A, Teixeira JP. Selected Peer-Reviewed Articles from the LPonTR 2008 Workshop. Journal of Low Power Electronics 2008, 4(3), 372–373.
• Gardiner KT, Yakovlev A, Bystrov A. A C-element latch scheme with increased transient fault tolerance for asynchronous circuits. In: 13th IEEE International On-Line Testing Symposium Proceedings. 2007, Heraklion, Crete, Greece: IEEE Computer Society.
• D'Alessandro C, Mokhov A, Bystrov A, Yakovlev A. Delay/Phase regeneration circuits. In: 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2007). 2007, Berkeley, California: IEEE Computer Society.
• Sokolov D, Bystrov A, Yakovlev A. Direct mapping of low-latency asynchronous controllers from STGs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2007, 26(6), 993-1009.
• D'Alessandro C, Bystrov A, Yakovlev A. Improved phase-encoding signalling. Electronics Letters 2007, 43(4), 216-217.
• Shang D, Yakovlev A, Koelmans A, Sokolov D, Bystrov A. Registers for Phase Difference Based Logic. IEEE Transactions on Very Large Scale Integration Systems 2007, 15(6), 720-724.
• Shang D, Burns F, Bystrov A, Koelmans A, Sokolov D, Yakovlev A. High-security asynchronous circuit implementation of AES. IEE Proceedings - Computers and Digital Techniques 2006, 153(2), 71-77.
• Shang D, Yakovlev A, Burns F, Xia F, Bystrov A. Low-Cost Online Tesing of Asynchronous Handshakes. In: 11th IEEE European Test Symposium (ETS'06). 2006, Southampton, UK: IEEE.
• D'Alessandro C, Shang D, Bystrov A, Yakovlev A, Maevsky O. Multiple-rail phase-encoding for NoC. In: 12th IEEE International Symposium on Asynchronous Circuits and Systems. 2006, Grenoble: IEEE.
• Koppad D, Sokolov D, Bystrov A, Yakovlev A. Online testing by protocol decomposition. In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006). 2006, Lake Como, Italy: IEEE.
• Sokolov D, Murphy J, Bystrov A, Yakovlev A. Design and analysis of dual-rail circuits for security applications. IEEE Transactions on Computers 2005, 54(4), 449-460.
• Koppad D, Bystrov A, Yakovlev A. Off-line testing of asynchronous circuits. In: 18th International Conference on VLSI Design. 2005, Kolkata, India: IEEE Computer Society.
• Shang D, Bystrov A, Yakovlev A, Koppad D. On-line testing of globally asynchronous circuits. In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005). 2005, Saint-Raphaël, French Riviera, France: IEEE.
• Murphy J, Bystrov A, Yakovlev A. Power-balanced self checking circuits for cryptographic chips. In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005). 2005, Saint Raphael, French Riviera, France: IEEE.
• Murphy J, Bystrov A, Yakovlev A. Power-balanced self checking circuits for cryptographic chips. In: 11th IEEE International On-Line Testing Symposium. 2005, Saint Raphaël, France: IEEE Computer Society.
• D'Alessandro C, Shang D, Bystrov A, Yakovlev A. PSK Signalling on NoC Buses. In: Integrated circuit and system design power and timing modeling, optimization and simulation : 15th international workshop, PATMOS 2005. 2005, Leuven, Belgium: Berlin.
• Shang D, Burns F, Bystrov A, Koelmans A, Sokolov D, Yakovlev A. A low and balanced power implementation of the AES security mechanism using self-timed circuits. In: Integrated circuit and system design: power and timing modeling, optimization and simulation. 14th International Workshop, PATMOS 2004. 2004, Santorinim, Greece: Springer.
• Yakovlev A, Furber S, Krenz R, Bystrov A. Design and analysis of a self-timed duplex communication system. IEEE Transactions on Computers 2004, 53(7), 798-814.
• Murphy J, Sokolov D, Bystrov A. Experiments with adding security to synchronous netlists. In: 15th UK Asynchronous Forum. 2004, Cambridge, UK.
• Sokolov D, Murphy J, Bystrov A, Yakovlev A. Improving the security of dual-rail circuits. In: Cryptographic Hardware and Embedded Systems - CHES 2004. 2004, Cambridge, MA: Springer.
• Bystrov A, Sokolov D, Yakovlev A. Low-latency control structures with slack. In: Ninth International Symposium on Asynchronous Circuits and Systems. 2003, Vancouver, Canada: IEEE Computer Society.
• Starodoubtsev N, Bystrov A, Yakovlev A. Monotonic circuits with complete acknowledgement. In: 9th International Symposium on Asynchronous Circuits and Systems (ASYNC 2003). 2003, Vancouver, Canada: IEEE Computer Society.
• Kinniment DJ, Maevsky OV, Bystrov A, Russell G, Yakovlev A. On-chip structures for timing measurement and test. Microprocessors and Microsystems 2003, 27(9), 473-483.
• Bystrov A, Sokolov D, Yakovlev A. OR-causality in low-latency asynchronous circuits. In: International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC). 2003, Vancouver, British Columbia, Canada.
• Sokolov D, Bystrov A, Yakovlev A. STG optimisation in the direct mapping of asynchronous circuits. In: Design, Automation and Test in Europe (DATE). 2003, Munich, Germany: IEEE.
• Madalinski A, Bystrov A, Khomenko V, Yakovlev A. Visualisation and resolution of encoding conflicts in asynchronous circuit design. In: 6th Conference on Design and Test in Europe (DATE03). 2003, Munich, Germany: IEE Proceedings: Computers and Digital Techniques.
• Madalinski A, Bystrov A, Khomenko V, Yakovlev A. Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design. IET Computers & Digital Techniques 2003, 150(5), 285-293.
• Maevsky O, Kinniment DJ, Yakovlev A, Bystrov A. Analysis of the oscillation problem in tri-flops. In: 2002 IEEE International Symposium on Circuits and Systems. 2002, Phoenix-Scottsdale, Arizona, USA: IEEE.
• Bystrov A, Yakovlev A. Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. In: 8th International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). 2002, Manchester, UK: IEEE Computer Society.
• Sokolov D, Bystrov A, Yakovlev A. Automated design of low-latency asynchronous circuits by direct mapping. In: Postgraduate Research Conference in Electronics, Photonics, Communications and Software (PREP). 2002, Nottingham, UK.
• Madalinski A, Bystrov A, Yakovlev A. ICU: A tool for Identifying State Coding Conflicts using STG unfoldings. University of Newcastle upon Tyne: School of Computing Science, 2002. CS-TR-773.
• Bystrov A, Sokolov D, Yakovlev A. Low-latency control structures with slack. In: 13th UK Asynchronous Forum. 2002, Cambridge.
• Kinniment DJ, Maevsky OV, Bystrov A, Russell G, Yakovlev A. On-chip structures for timing measurement and test. In: 8th International Symposium on Asynchronous Circuits and Systems (ASYNC 2002). 2002, Manchester, UK: IEEE Computer Society.
• Kinniment DJ, Bystrov A, Yakovlev A. Synchronization circuit performance. IEEE Journal of Solid-State Circuits 2002, 37(2), 202-209.
• Bystrov A, Yakovlev A. Synthesis of Asynchronous Circuits with Predictable Latency. In: 11th IEEE/ACM International Workshop on Logic and Synthesis (IWLS 2002). 2002, New Orleans, Louisiana, USA: IEEE Computer Society & ACM SIGDA.
• Abas MA, Bystrov A, Kinniment DJ, Maevsky OV, Russell G, Yakovlev AV. Time difference amplifier. Electronics Letters 2002, 38(23), 1437-1438.
• Sokolov D, Bystrov A, Yakovlev A. Tools for STG optimisation in the direct mapping of asynchronous circuits. In: Special Interest Group on Design Automation (SIGDA). 2002.
• Xia F, Yakovlev A, Shang D, Bystrov A, Koelmans A, Kinniment D. Asynchronous communication mechanisms using self-timed circuits. In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000). 2000, Eliat, Israel: IEEE Computer Society.
• Bystrov A, Kinniment D, Yakovlev A. Priority arbiters. In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000). 2000, Eliat, Israel: IEEE Computer Society.
• Starodoubtsev N, Bystrov A, Yakovlev A. Semi-modular latch chains for asynchronous circuit design. Lecture Notes in Computer Science: Integrated Circuit Design 2000, 1918, 168-177.
• Xia F, Yakovlev A, Bystrov A, Koelmans AM, Kinniment DJ, Shang D. An Asynchronous Communication Mechanism Using Self-timed Circuits. Newcastle upon Tyne: Department of Computing Science, University of Newcastle upon Tyne, 1999. Department of Computing Science Technical Report Series 686.
• Bystrov A, Kinniment DJ, Yakovlev A. Priority Arbiters. Newcastle upon Tyne: Department of Computing Science, University of Newcastle upon Tyne, 1999. Department of Computing Science Technical Report Series 687.
• Bystrov A, Almaini AEA. Testability and Test Compaction for Decision Diagram Circuits. IEE Proceedings - Circuits, Devices and Systems 1999, 146(4), 153-158.