Staff Profile

I am currently a Research Associate with the Microsystems Research Group, working on the project - Exploiting the dynamics of self-timed machine learning hardware (ESTEEM). This project specifically focuses on design and implementation of Tsetlin machine on flexible integrated circuit (IC).

Prior to my current position, I worked as a Lecturer with the School of Computer Engineering and Science, Shanghai University, from Jun 2019 to Feb 2024. During this period, I was engaged in several research projects, including hardware/software co-design for machine learning algorithms and design of silicon Physical Unclonable Function (PUF) towards hardware security. I teached several undergraduate modules, including Computer Organization, Signal Processing and Data Mining.

I received my PhD degree from the University of Southampton, in 2019. My PhD study focused on IC design for reliability specifically considering CMOS ageing effects.

I have published over 20 conference and journal papers in the areas of IC and machine learning.

Qualifications

• 2014-2019: PhD in Electronic and Electrical Engineering, University of Southampton, UK. Thesis title: "Bias Temperature Instability Ageing-reslilient Digital System Design".
• 2013-2014: MSc in Microelectronics Systems Design, University of Southampton, UK.
• 2009-2013: BEng in Telecommunication Engineering, Huazhong University of Science and Technology, China.
• 2012-2013: BEng in Electronic and Electrical Engineering, University of Birmingham, UK.

• Hardware/software co-design for machine learning
• Very Large Scale Integration (VLSI) design
• Hardware security, specifically Physical Unclonable Function (PUF)
• Integrated circuit reliability.

• Articles

  • Duan S, Sai G. BTI aging-based physical cloning attack on SRAM PUF and the countermeasure. Analog Integrated Circuits and Signal Processing 2023, 117, 45-55.
  • Mispan, MS, Duan, S, Halak, B, Zwolinski, M. A reliable PUF in a dual function SRAM. Integration the VLSI journal 2019, 68, 12-21.
  • Lu, Y, Duan, S, Halak, B, Kazmierski, TJ. A cost-efficient error-resilient approach to distributed arithmetic for signal processing. Microelectronics Reliability 2019, 93, 16-21.
  • Duan, S, Halak, B, Zwolinski, M. Lifetime reliability-aware digital synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2018, 26(11), 2205-2216.

• Book Chapter

  • Duan, S, Zwolinski, M, Halak, B. Ageing-Aware Logic Synthesis. In: Ageing of Integrated Circuits. Cham: Springer, 2019, pp.113-145.

• Conference Proceedings (inc. Abstracts)

  • Wu Y, Sai G, Duan S. Work-in-Progress: Accelerated Matrix Factorization by Approximate Computing for Recommendation System. In: International Conference on Embedded Software (EMSOFT). 2022, Shanghai, China: IEEE.
  • Liu X, Sai G, Duan S. Hardware Acceleration for 1D-CNN Based Real-Time Edge Computing. In: 19th IFIP WG 10.3 International Conference on Network and Parallel Computing (NPC 2022). 2022, Jinan, China: Springer.
  • Duan S, Sai G. A secure authentication scheme based on differential public PUF. In: 19th ACM International Conference on Computing Frontiers (CF ’22). 2022, Turin, Italy: ACM.
  • Duan, S, Wang, P, Sai, G. BTI Aging Monitoring based on SRAM Start-up Behavior. In: IEEE 29th Asian Test Symposium. 2020.
  • Duan, S, Halak, B, Zwolinski, M. Cell flipping with distributed refresh for cache ageing minimization. In: IEEE 27th Asian Test Symposium (ATS). 2018.